As a Qualcomm Hardware Engineering Intern, you’ll have the opportunity to push the boundaries of what exists and help establish the new standards for tomorrow. You will leverage your electrical and/or computer engineering degree to work on one of the following Qualcomm multi-disciplinary teams: System (architecture, modeling, power, thermal as well as silicon profiling ), Front-end Design (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design-for-Test (DFT), Physical Design (Place & route, CTS, timing closure), Pre-silicon Verification (DV), Emulation, Post-silicon Validation (VI), CAD, GPU Design, and Machine Learning.   

Possible Internship Locations:

• San Diego, CA

• Boulder, CO

• Boxborough, MA

• Santa Clara, CA

• Austin, TX

• Raleigh, NC

Minimum Qualifications

• Currently enrolled in a bachelor’s, master’s, or Ph.D. degree program in computer engineering, computer science, electrical engineering, or a related field 

• 1+ years of academic experience with programming languages such as C, C++, Python, Perl, Verilog, SystemVerilog etc. 

• Must be available for 11 – 14 weeks during Summer 2025 (May-September) with a graduation date of December 2025 or later

Preferred Qualifications

• Candidates actively pursuing a degree with an anticipated graduation within the upcoming year preferred Dec 2025 to June 2026.

• Currently enrolled in a Master’s or PhD degree program in computer engineering, electrical engineering, or a related field 

• Candidates with academic or professional experience in one or more of the following technical tracks:

GPU

• Engineering design and development in MSM SOC (Mobile Station Modem System on chips) and Chipset Architecture

• ASIC implementation of Image processing Camera IP

• GPU pipeline validation (stimulus generators, checkers, monitors, drivers and models for power/performance)

• Graphics power analysis & optimization (Vulkan)

• C, Perl, Verilog, System Verilog, C++, Python

CPU

• Validation of concepts and high-level system requirements related to CPU and SOC level micro-architecture

• Develop detailed test and coverage plans based on the architecture and micro-architecture

• Develop verification methodology, ensuring scalable and portable environment

• Develop verification plans and test benches

• Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features, debug of the test failures

• Verification methodologies and tools such as simulators, coverage collection, gate level simulation, waveform viewers

• C, C++, Python

Digital Design/DV

• ​RTL development for modem physical and MAC layer processing

• Development of verification components using System Verilog and UVM

• Participating in model cellular modem datapaths for bit exact correctness and verification of wireless modem

• Digital design fundamentals and digital signal processing

• Wireless communication, digital communication, communication theory

• Cellular (LTE, 5G) and WiFi (802.11 be)

• C, Python, Perl, Verilog, System Verilog, C++, Matlab