General Summary:
• Extensive experience in Place & Route with FC or Innovus is an absolute must
• Complete ASIC flow with low power, performance and area optimization techniques
• Experience with STA using Primetime and/or Tempus is required
• Proficient in constraint generation and validation
• Experience of multiple power domain implementation with complex UPF/CPF definition required
• Formal verification experience (Formality/Conformal)
• Perl/Tcl, Python, C++ skills are needed
• Strong problem solving and ASIC development/debugging skills
• Experience with CPU micro-architecture and their critical path
• Low power implementation techniques experience
• High speed CPU implementation
• Clock Tree Implementation Techniques for High Speed Design Implementation are required
• Exposure to Constraint management tool and Verilog coding experience
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.• Extensive experience in Place & Route with FC or Innovus is an absolute must
• Complete ASIC flow with low power, performance and area optimization techniques
• Experience with STA using Primetime and/or Tempus is required
• Proficient in constraint generation and validation
• Experience of multiple power domain implementation with complex UPF/CPF definition required
• Formal verification experience (Formality/Conformal)
• Perl/Tcl, Python, C++ skills are needed
• Strong problem solving and ASIC development/debugging skills
• Experience with CPU micro-architecture and their critical path
• Low power implementation techniques experience
• High speed CPU implementation
• Clock Tree Implementation Techniques for High Speed Design Implementation are required
• Exposure to Constraint management tool and Verilog coding experience
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