In this role you will be working with the IP designers, Verification engineers, Validation engineers, Firmware and SoC engineers to validate the next generation Bluetooth and other PAN IPs on Qualcomm proprietary as well as industry standard emulation platforms.  You’ll be responsible for taking the IP through the entire FPGA design implementation cycle.  You’ll code the necessary emulation specific RTL needed to exercise the IP.  You’ll be directly responsible for adapting the design for FPGA, come up the timing constraints, run synthesis, floorplan the design for the target FPGA, run place & route tools and generate bit files.  You’ll work closely with validation and Firmware engineers to instrument test structures for observing and logging signals during debug using ILA/Chipscope, Logic Analyzer, Oscilloscope and other lab equipment.

Skills/Experience

• 3-6 years of hands-on experience in implementing designs on FPGA

• Strong expertise in RTL coding of complex designs using Verilog/SV

• Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure, bitfile generation

• Strong proficiency with FPGA EDA tools: Synplify, Vivado, ISE, Chipscope

• Knowledge of latest FPGA architectures and partitioning designs across multiple FPGAs

• Exposure to scripting languages

• Familiarity with lab equipment

• Familiarity with interface protocols desired

• Strong debugging, analytical and written/oral communication skills

Minimum Qualifications

• Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field

• 3 years of industry experience in Digital Design

Preferred Qualifications

• Exposure to Bluetooth/BLE Technologies and scripting languages like Perl and/or Python