Power and Limits Management Architect (Multiple Locations) in Santa Clara, CA at honor foundations

Date Posted: 11/5/2024

Job Snapshot

  • Employee Type:
    Full-Time
  • Job Type:
  • Experience:
    Not Specified
  • Date Posted:
    11/5/2024

Job Description


Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Responsibilities

Candidate will be responsible for developing next generation power and limits system. With HPC, AI, and automotive system become so compute intense, the thermal and electrical constrained performance is becoming the bottleneck. A new system needs to be defined to have maximum performance while meet the thermal and power envelop. A fast DCVS system is also needed to make the transient response of the power delivery system to be able to support high frequency CPU, GPU, and NSP. The candidate will be defining the power and limit system to have optimal system performance while enforce the thermal and electrical limits with minimum SW intervention. This role will require the candidate to understand and work on all aspects of power control and limits architecture, micro architecture and interactions with system, SW and product team.

Skills/Experience

  • 10+ years of strong experience in power and limits system
  • Familiar with UPF and power domain crossing
  • Experience in low power design methodology and clock domain crossing designs
  • Proficient in Perl, Python scripting
  • Expertise in post-Si debug is a plus

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$142,500.00 - $247,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.

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